The present application relates to a semiconductor structure and a method of forming the same. More particularly, the present application relates to a low resistance interconnect structure containing a combined via level/line level interconnect structure and an overlying line level interconnect structure both of which include a metal or metal alloy having a bamboo microstructure. The present application also provides a method of forming the same.
Generally, semiconductor devices include a plurality of circuits that form an integrated circuit (IC) fabricated on a semiconductor substrate. A complex network of signal paths will normally be routed to connect the circuit elements distributed on the surface of the substrate. Efficient routing of these signals across the device requires formation of multilevel or multilayered schemes, such as, for example, single or dual damascene wiring structures. The wiring structure, which may also be referred to as an interconnect structure, typically includes copper, Cu, since Cu based interconnects provide higher speed signal transmission between large numbers of transistors on a complex semiconductor chip as compared with aluminum, Al, based interconnects.
Within a typical interconnect structure, metal vias run perpendicular to the semiconductor substrate and metal lines run parallel to the semiconductor substrate. Further enhancement of the signal speed and reduction of signals in adjacent metal lines (known as “crosstalk”) are achieved in today's IC product chips by embedding the metal lines and metal vias in a dielectric material having a dielectric constant of less than 4.0.
As the dimensions of the interconnect structures become smaller, the resistivity of the interconnect structures increases dramatically. This becomes a challenge for the development of current and future semiconductor nodes. As such, there is a need for providing interconnect structures having low resistance which can be used in today's and future semiconductor technology nodes.